In recent years, miniaturization of semiconductor integrated circuit elements has reduced the intervals between elements and between wires internally connecting the elements together. This has disadvantageously increased the capacity between the wires to reduce a speed at which signals are propagated. Thus, examinations have been conducted of a method of forming an air gap between the wires to reduce the capacity. With reference to FIGS. 16A, 16B, 16C, 16D, 16E, 17A, 17B, 17C, and 17D, description will be given of a conventional method of manufacturing a semiconductor device having the air gap formed therein.
FIGS. 16A, 16B, 16C, 16D, 16E, 17A, 17B, 17C, and 17D are sectional views illustrating steps of the conventional method of manufacturing the semiconductor device.
First, as shown in FIG. 16A, an interlayer insulating film 2 and an inter-wire insulating film 3 are deposited on a surface of a semiconductor substrate 1. Wiring grooves 4 are formed in an upper part of a film stack of the interlayer insulating film 2 and the inter-wire insulating film 3 by photolithography and dry etching.
Then, as shown in FIG. 16B, a barrier film 5 and a Cu film 6 are sequentially deposited on the inter-wire insulating film 3 and inside the wiring grooves 4. Parts of the barrier film 5 and Cu film 6 which stick out from the wiring grooves 4 are then removed by CMP to form lower wires 7.
Then, as shown in FIG. 16C, a cap film 8 is selectively grown on surfaces of the lower wires 7.
Then, as shown in FIG. 16D, a resist pattern 9 is formed at a predetermined position on surfaces of the inter-wire insulating film 3 and the cap film 8. The purpose of formation of the resist pattern 9 will be described below in detail.
Then, as shown in FIG. 16E, the interlayer insulating film 2 and the inter-wire insulating film 3 are partly etched through the cap film 8 and the resist pattern 9 as a mask. Gaps 10 are thus formed between the lower wires 7.
Then, as shown in FIG. 17A, the resist pattern 9 is removed.
Then, as shown in FIG. 17B, an interlayer insulating film 11 is deposited on the surfaces of the inter-wire insulating film 3 and the cap film 8 under a low step coverage condition. Thus, the top of the gaps 10 is closed by the interlayer insulating film 11 to form air gaps 12 between the lower wires 7.
Then, as shown in FIG. 17C, an inter-wire insulating film 13 is deposited on a surface of the interlayer insulating film 11. Lithography and dry etching are then used to form a via hole 14 inside the interlayer insulating film 11 and inter-wire insulating film 13 and to form a wiring groove 15 in an upper part of the interlayer insulating film 11 and inter-wire insulating film 13.
Finally, as shown in FIG. 17D, a barrier film 16 and a Cu film 17 are deposited on a surface of the inter-wire insulating film 13, inside the via hole 14, and inside the wiring groove 15. Parts of the barrier film 16 and the Cu film 17 which stick out from the wiring groove 15 are removed by CMP to form a via 18 and an upper wire 19.
Now, the purpose of the formation of the resist pattern 9 will be described. There are two reasons why the resist pattern 9 is formed.
The first reason is that “the resist pattern 9 can prevent recesses and protrusions from being created”. When the intervals between the lower wires 7 are small, the interlayer insulating film 11 completely blocks the top of the gaps 10 to form the well-defined air gaps 12. However, if the intervals between the lower wires 7 are large, the top of the gaps 10 is prevented from being closed even with the deposition of the interlayer insulating film 11. This results in the creation of large recesses and protrusions. When such recesses and protrusions are formed in a semiconductor device, the dimensional controllability of photolithography may be degraded. For example, the width of the wires may be larger or smaller than a designed value. This phenomenon may reduce the yield and reliability of the semiconductor device. Thus, if the intervals between the lower wires 7 are large, the resist pattern 9 needs to be formed in the appropriate areas to prevent the formation of the gaps 10.
The second reason is that “the resist pattern 9 can prevent the via and the air gap from contacting each other”. Without the resist pattern 9, the air gaps 12 are also formed around the periphery of the via 18. In this situation, when the lower wire 7 and the via 18 are misaligned, the via 18 may contact the air gap 12. In this case, in the steps shown in FIGS. 17C and 17D, various substances may flow into the air gap 12, reducing the yield and reliability of the semiconductor device.
To prevent this phenomenon, the resist pattern 9 needs to be formed in the area where the via 18 is formed, to adjust the positions where the gaps 10 are formed (see, for example, Patent Document 1).